The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

Feb. 24, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Albrecht Mayer, Deisenhofen, DE;

Patrik Eder, Taufkirchen, DE;

Kajetan Nuernberger, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 15/7807 (2013.01); G06F 9/30003 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45591 (2013.01);
Abstract

In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.


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