The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2025

Filed:

May. 09, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Madhu Yashwanth Boenapalli, Hyderabad, IN;

Kaustub Naidu Paila Ram, Hyderabad, IN;

Sravani Devineni, Hyderabad, IN;

Sai Praneeth Sreeram, Anantapur, IN;

Vinod Kumar Kuruma, Jogulamba Gadwal, IN;

Rajendra Varma Pusapati, Hyderabad, IN;

Surendra Paravada, Hyderabad, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A Peripheral Component Interconnect Express (PCIe) system is configured to determine when the frequency of link speed switching needed to service incoming and upcoming client requests is too high. The system is also configured to determine a modest link speed to be used to service incoming and upcoming client requests in cases where the link speed switching that will be needed is too high and causes the incoming and upcoming client requests to be serviced at the modest link speed instead of at the link speeds associated with the predefined BWs of the clients. By doing this when the frequency of link speed switching needed is too high, the PCIe system achieves better throughput while also reducing power consumption.


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