The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Jan. 08, 2025
Applicant:

Taiyuan University of Technology, Shanxi, CN;

Inventors:

Shengbo Sang, Taiyuan, CN;

Fan Zhang, Taiyuan, CN;

Jianlong Ji, Taiyuan, CN;

Xiaojie Chai, Taiyuan, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 71/13 (2023.01); B33Y 10/00 (2015.01); B33Y 40/10 (2020.01); B33Y 50/02 (2015.01); B33Y 80/00 (2015.01);
U.S. Cl.
CPC ...
H10K 71/135 (2023.02); B33Y 10/00 (2014.12); B33Y 40/10 (2020.01); B33Y 50/02 (2014.12); B33Y 80/00 (2014.12);
Abstract

The embodiments of the present disclosure relate to the technical field of a flexible semiconductor 3D additive material, in particular to a system for printing and discharging of a flexible semiconductor 3D additive material and a control method thereof. Ink materials corresponding to different layers of a flexible semiconductor to be printed are pre-treated prior to entering troughs. The ink materials after the pretreatment flow into the multi-channel troughs, the corresponding ink materials are controlled to be sequentially extruded by gases in the corresponding troughs, intertwined and injected into interfaces, and stacked to form a stacked layer structure at end of printheads connected with the interfaces to complete discharging and printing, thereby realizing simultaneous printing of the ink materials of different viscosities and fluidities, improving the printing speed, and realizing direct printing of a sandwich structure of a semiconductor device.


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