The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Apr. 01, 2024
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventor:

Biqin Huang, Torrance, CA (US);

Assignee:

HRL LABORATORIES, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/83 (2025.01); H01L 21/761 (2006.01); H10D 12/01 (2025.01); H10D 30/00 (2025.01); H10D 30/01 (2025.01); H10D 30/87 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01); H10D 62/834 (2025.01); H10D 30/62 (2025.01);
U.S. Cl.
CPC ...
H10D 30/202 (2025.01); H01L 21/761 (2013.01); H10D 12/031 (2025.01); H10D 30/01 (2025.01); H10D 30/87 (2025.01); H10D 62/114 (2025.01); H10D 62/117 (2025.01); H10D 62/149 (2025.01); H10D 62/221 (2025.01); H10D 62/822 (2025.01); H10D 62/83 (2025.01); H10D 62/8303 (2025.01); H10D 62/8325 (2025.01); H10D 62/834 (2025.01); H10D 30/62 (2025.01); H10D 62/121 (2025.01);
Abstract

Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.


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