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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12324160 B1

PDFFull Text
Date of Patent:
Jun. 03, 2025

Filed:

Dec. 26, 2023

Semiconductor memory device and manufacturing method thereof

Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jae Taek Kim, Icheon-si, KR;

Hye Yeong Jung, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:

WILLIAM PARK & ASSOCIATES LTD.

Primary Examiner:

Richard A Booth

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/50 (2023.01); H10B 63/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 63/30 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

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