Clock correction method and clock correction circuit

Abstract

A clock correction method suitable for a communication device comprising a clock correction circuit comprises: in response to the communication device being enabled and entering an active mode, calculating, by the clock correction circuit, a clock-period ratio between a slow clock and a fast clock; in response to the communication device operating in a power-saving mode for a power-saving period, counting at least one rising edge of the slow clock received by the clock correction circuit during the power-saving period, as a cumulative number; in response to the communication device switching to an active mode, calculating the difference between an internal time of the communication device and a reference time of another communication device as a time offset; and in the active mode, adjusting, by the clock correction circuit, the clock-period ratio by using a compensation value related to the clock-period ratio, the cumulative number and the time offset.