The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

May. 31, 2021
Applicants:

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jie Lei, Beijing, CN;

Zouming Xu, Beijing, CN;

Jian Tian, Beijing, CN;

Chunjian Liu, Beijing, CN;

Xintao Wu, Beijing, CN;

Jie Wang, Beijing, CN;

Jianying Zhang, Beijing, CN;

Yajun Ma, Beijing, CN;

Zhi Zhang, Beijing, CN;

Zhentao Li, Beijing, CN;

Li Yin, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/075 (2006.01); H01L 25/16 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H01L 25/0753 (2013.01); H01L 25/167 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01);
Abstract

An array substrate () and a display device. The array substrate () includes a bonding area (). The array substrate () includes a substrate (), a first conductive layer () on the substrate (), a first insulating layer () on one side of the first conductive layer () away from the substrate (), and a second conductive layer () on one side of the first insulating layer () away from the substrate (). The bonding area () is provided with bonding pins (), and the bonding pin () includes a first conductive portion () and a second conductive portion () located on the side of the first conductive portion () away from the substrate (), the first conductive portion () is located in the first conductive layer (), the second conductive portion () is located in the second conductive layer (), and the first conductive portion () is in direct contact with the second conductive portion (). The first insulating layer () is provided with at least one first opening (), and the orthographic projection of each of the first openings () on the substrate () covers the orthographic projections of the plurality of bonding pins () on the substrate ().


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