The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

May. 28, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Justin Wong, Concord, CA (US);

Ehud Chatow, Palo Alto, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); B24B 37/005 (2012.01); H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); B24B 37/005 (2013.01); H01L 21/02057 (2013.01); H01L 21/3212 (2013.01); H01L 21/67046 (2013.01); H01L 21/67253 (2013.01); H01L 21/67259 (2013.01); H01L 21/67288 (2013.01);
Abstract

Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished.


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