The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2025
Filed:
May. 25, 2023
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Lalit Gupta, Fremont, CA (US);
Jason Golbus, Palo Alto, CA (US);
Jesse San-Jey Wang, Santa Clara, CA (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1069 (2013.01); G11C 7/1063 (2013.01); G11C 7/1066 (2013.01); G11C 7/18 (2013.01);
Abstract
Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.