The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2025

Filed:

Feb. 22, 2023
Applicant:

Dell Products, L.p., Hopkinton, MA (US);

Inventors:

Ro Monserrat, Medfield, MA (US);

Jonathan Krasner, Coventry, RI (US);

Assignee:

Dell Products, L.P., Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3246 (2019.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3246 (2013.01); G06F 9/4881 (2013.01); G06F 9/526 (2013.01); G06F 13/4027 (2013.01); G06F 2209/521 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A pair of compute nodes, each having a separate PCIe root complex, are interconnected by a PCIe Non-Transparent Bridge (NTB). An instance of a NTB monitoring process is started for each root complex, and the CPU affinity of the NTB monitoring processes are set to cause each NTB monitoring process to be executed on CPU resources of each respective CPU root complex. The NTB monitoring process on a given root complex is allowed to sleep until a triggering event occurs that causes the NTB monitoring process to wake and determine the state of the NTB. One such triggering event is a failure of an atomicity algorithm on the compute node to obtain a lock on peer memory in connection with implementing an atomic read operation on the peer memory over the NTB.


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