The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 16, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chul Joon Heo, Busan, KR;

Kyung Bae Park, Hwaseong-si, KR;

Sung Young Yun, Suwon-si, KR;

Hyeongju Kim, Changwon-si, KR;

Feifei Fang, Suwon-si, KR;

Hwijoung Seo, Hwaseong-si, KR;

Juhyung Lim, Suwon-si, KR;

Taejin Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H10K 39/32 (2023.01); H10K 50/11 (2023.01); H10K 59/35 (2023.01); H10K 59/60 (2023.01); H10K 101/40 (2023.01);
U.S. Cl.
CPC ...
H10K 59/60 (2023.02); H10K 39/32 (2023.02); H10K 50/11 (2023.02); H10K 59/353 (2023.02); H10K 2101/40 (2023.02);
Abstract

A sensor-embedded display panel includes a substrate, a light emitting element on the substrate and including a light emitting layer, and a photosensor on the substrate and including a photoelectric conversion layer in parallel with the light emitting layer along an in-plane direction of the substrate, wherein the light emitting element and the photosensor each include a separate portion of a first common auxiliary layer that is a single piece of material that extends continuously on the light emitting layer and the photoelectric conversion layer, and a separate portion of a common electrode on the first common auxiliary layer and is configured to apply a common voltage to both the light emitting element and the photosensor, and the photoelectric conversion layer includes a sequential stack from the first common auxiliary layer of a first n-type semiconductor layer, a second n-type semiconductor layer, and a p-type semiconductor layer.


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