The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2025
Filed:
Apr. 10, 2023
China Resources Microelectronics (Chongqing) Co., Ltd., ChongQing, CN;
Fei Luo, ChongQing, CN;
Yuling Tang, ChongQing, CN;
Mingjiang He, ChongQing, CN;
Jianwen Tan, ChongQing, CN;
CHINA RESOURCES MICROELECTRONICS (CHONGQING) CO., LTD., ChongQing, CN;
Abstract
An SGT MOSFET comprising a substrate, an epitaxial layer, a masking dielectric layer, an interlayer dielectric layer, a source lead-out contact hole, and a source conductive layer and a method for manufacturing the SGT MOSFET are provided. The epitaxial layer is on an upper surface of the substrate and comprises a cellular trench structure, a terminal lead-out structure, a source lead-out structure, a body region, and a source region. The source lead-out structure comprises a source lead-out conductive layer. The masking dielectric layer and the interlayer dielectric layer are sequentially stacked above the epitaxial layer. The source lead-out contact hole penetrates the interlayer dielectric layer and the masking dielectric layer and extends into the source lead-out conductive layer, The source conductive layer fills the source lead-out contact hole. The masking dielectric layer is formed between the interlayer dielectric layer and the epitaxial layer and masks the third dielectric layer.