The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Apr. 13, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ki Wook Jung, Seoul, KR;

Dong Oh Kim, Daegu, KR;

Seok Han Park, Hwaseong-si, KR;

Chan Sic Yoon, Anyang-si, KR;

Ki Seok Lee, Hwaseong-si, KR;

Ho In Lee, Suwon-si, KR;

Ju Yeon Jang, Hwaseong-si, KR;

Je Min Park, Suwon-si, KR;

Jin Woo Hong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); C01G 23/053 (2006.01); H01L 23/535 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10D 62/17 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); C01G 23/0536 (2013.01); H01L 23/535 (2013.01); H10B 12/033 (2023.02); H10B 12/0385 (2023.02); H10B 12/09 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10D 62/221 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); C01P 2004/52 (2013.01); C01P 2004/62 (2013.01); C01P 2004/64 (2013.01); C01P 2006/12 (2013.01); H10D 84/0177 (2025.01);
Abstract

A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.


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