The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Apr. 12, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:
Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/80 (2006.01); H03M 1/06 (2006.01); H03M 1/68 (2006.01); H03M 1/74 (2006.01); H03M 1/78 (2006.01);
U.S. Cl.
CPC ...
H03M 1/802 (2013.01); H03M 1/0624 (2013.01); H03M 1/68 (2013.01); H03M 1/747 (2013.01); H03M 1/785 (2013.01);
Abstract

A digital-to analog converter (DAC) includes an unary cell comprising unary slices, the unary slices are coupled in parallel, an intermediate significant bit (ISB) cell comprising ISB slices, the ISB slices are coupled in parallel, and a least significant bit (LSB) cell comprising LSB slices, the LSB slices are coupled in parallel, the unary cell, the ISB cell and the LSB cell each being coupled to each other, each of the unary slices comprising a set of cross-coupled capacitive elements including first capacitive elements having a first end coupled to a node positioned between a first pair of transistors and a second end coupled to a node positioned between a second pair of transistors, and second capacitive elements having a first end coupled to a node positioned between a third pair of transistors and a second end coupled to a node positioned between a fourth pair of transistors.


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