The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Apr. 26, 2022
Applicant:

National Research Council of Canada, Ottawa, CA;

Inventor:

Brent Carlson, Penticton, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/093 (2006.01); H03L 7/14 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); H03L 7/145 (2013.01);
Abstract

A digital clean-up oscillator and associated method are provided for cleaning jitter from a noisy clock signal, comprising receiving a reference clock oscillator signal and the noisy clock signal to be cleaned: measuring the frequency of the reference clock signal in the time domain of the noisy clock signal: filtering any frequency variations from the measured frequency of the reference clock signal on timescales shorter than a phase change interval Tau_clean over which jitter in the noisy clock signal is to be cleaned; generating a phase increment signal DDS_pinc based on the measured and filtered frequency of the reference clock signal: clocking the phase increment signal DDS_pinc with the reference clock signal for generating an output digital phase ramp signal φ_DDS(t) that tracks the frequency of the noisy clock signal with phase wander removed on timescales less than the phase change interval Tau_clean; and converting the output digital phase ramp signal φ_DDS(t) to an output jitter-cleaned time domain clock signal frequency locked to the noisy clock signal.


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