The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

May. 27, 2024
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Seung Ho Lee, Seoul, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 19/00 (2006.01); H03K 19/017 (2006.01); H03K 19/17788 (2020.01);
U.S. Cl.
CPC ...
H03K 19/00315 (2013.01); H03K 19/0005 (2013.01); H03K 19/01742 (2013.01); H03K 19/17788 (2013.01);
Abstract

A memory system may include a memory device and a memory controller. The memory device may be configured to store data. The memory controller may be configured to communicate with the memory device by an input/output driving circuit. The input/output driving circuit comprises a pull-down driver and a gate control logic. The pull-down driver may include a first transistor and a second transistor which are electrically coupled between a pad and a ground node. The gate control logic including a third transistor and a fourth transistor which are electrically coupled between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage. The source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.


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