The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 06, 2023
Applicant:

Huawei Digital Power Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Xinyu Yu, Shanghai, CN;

Fei Xu, Shanghai, CN;

Kai Xin, Shanghai, CN;

Zhiwu Xu, Shenzhen, CN;

Lin Li, Shanghai, CN;

Haibin Guo, Dongguan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 7/487 (2007.01); H02M 1/12 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H02M 7/487 (2013.01); H02M 1/12 (2013.01); H02M 7/53871 (2013.01);
Abstract

Example three-level inverters, control methods, and systems are provided. One example three-level inverter includes a first bus capacitor, a second bus capacitor, a power conversion circuit, and a controller. The first bus capacitor is connected in the middle of the current bus and the power conversion circuit. The power conversion circuit is configured to convert a direct current into a three-phase alternating current for output. The controller is configured to determine a balance reference by using a difference between absolute values of voltages of the positive and negative direct current buses and an even harmonic current in a grid-connected current, where the balance reference is used to enable the three-level inverter to generate a current signal for balancing the voltages of the positive and negative direct current buses.


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