The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 01, 2024
Applicant:

Dell Products, L.p., Hopkinton, MA (US);

Inventors:

Rong Yu, West Roxbury, MA (US);

Lixin Pang, Needham, MA (US);

Assignee:

Dell Products, L.P., Hopkinton, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0631 (2013.01); G06F 3/0689 (2013.01);
Abstract

As front-end write IO operations occur, the front-end write IO operations are allocated slots of global memory and mapped to slices of back-end tracks. A back-end write destage manager allocates back-end slices to aging buckets based on the number of write operations pending destage for the given back-end slice. As global memory destage pressure increases, the back-end write destage manager uses a weighted bucket table to increase the weight back-end slices with larger numbers of front-end tracks that are occupying the larger slots of global memory. This results in back-end slices that are owed data from front-end tracks occupying larger front-end slot sizes to be placed in aging buckets with shorter aging times. These back-end slices are thus more quickly selected to be destaged, thus causing a larger percentage global memory slots of the largest slot size to be made available to be allocated to subsequent host IO write operations.


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