The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Aug. 12, 2024
Applicant:

China Jiliang University, Zhejiang, CN;

Inventors:

Yinglian Jin, Zhejiang, CN;

Binrui Wang, Zhejiang, CN;

Haochun Wang, Zhejiang, CN;

Kun Zhou, Zhejiang, CN;

Shanqiang Wu, Zhejiang, CN;

Wei Song, Zhejiang, CN;

Tao Zheng, Zhejiang, CN;

Xianlei Chen, Zhejiang, CN;

Assignee:

CHINA JILIANG UNIVERSITY, Hangzhou, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
G06F 13/20 (2013.01); G06F 2213/40 (2013.01);
Abstract

A synchronization optimization method for EtherCAT master slaves is provided. By capturing a time when a master sends a data frame, a time when receives, and a time when a reference slave receives the data frame, a transmission delay is calculated. A compensated transmission delay is obtained. A time taken for a data frame to leave a parent port and return to the same parent port, a transmission delay, a clock offset, and a clock drift are calculated. The clock drift is compensated. A new clock offset is obtained by subtracting the compensated clock drift from the clock offset and written into the non-reference slave for compensation to complete a synchronization optimization. The present application reduces the clock drift and enables the master to compensate for the clock drift of each slave more rapidly.


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