The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Dec. 20, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Timothy D. Anderson, University Park, TX (US);

Joseph Raymond Michael Zbiciak, San Jose, CA (US);

Kai Chirca, Dallas, TX (US);

Daniel Brad Wu, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 12/0862 (2016.01); G06F 12/0882 (2016.01); G06F 12/0891 (2016.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 9/467 (2013.01); G06F 9/4881 (2013.01); G06F 12/0862 (2013.01); G06F 12/0882 (2013.01); G06F 12/0891 (2013.01); G06F 12/1009 (2013.01); H03M 13/1575 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01);
Abstract

A method includes receiving, by a memory management unit (MMU) comprising a translation lookaside buffer (TLB) and a configuration register, a request from a processor core to directly modify an entry in the TLB. The method also includes, responsive to the configuration register having a first value, operating the MMU in a software-managed mode by modifying the entry in the TLB according to the request. The method further includes, responsive to the configuration register having a second value, operating the MMU in a hardware-managed mode by denying the request.


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