The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2025
Filed:
Feb. 22, 2023
Sma Solar Technology Ag, Niestetal, DE;
Uwe Stickelmann, Kaufungen, DE;
SMA Solar Technology AG, Niestetal, DE;
Abstract
A method for testing an inverter having a bridge comprising a first switch (T) arranged between a positive connection (DC+) of a divided link circuit, having a center point (M), and a positive inner connection (PI), a second switch (T) arranged between the positive inner connection (PI) and a bridge output (BR), a third switch (T) arranged between the bridge output (BR) and a negative inner connection (NI), a fourth switch (T) arranged between the negative inner connection (NI) and a negative connection (DC−) of the divided link circuit, a fifth switch (T) arranged between the center point (M) and the positive inner connection (PI), and a sixth switch (T) arranged between the center point (M) and the negative inner connection (NI) is disclosed. A grid filter having a filter inductor (LF) and a filter capacitor (CF) is connected to the bridge output (BR). The method comprises applying a link circuit voltage to the divided link circuit, while the bridge output (BR) is isolated from a connected grid using the connected grid filter, fully discharging the filter capacitor (CF), closing the first switch (T) and the sixth switch (T), while the fourth switch (T) and the fifth switch (T) are open, subsequently clocking the second switch (T) using a plurality of short pulses, wherein the duty cycle of the short pulses is predetermined between 1% and 5%, subsequently to the clocking determining a voltage dropped across the filter capacitor (CF) and identifying a fault state of the bridge when the voltage dropped is outside of a voltage window with an upper window limit and a lower window limit. An inverter is also disclosed, which has a control system designed and set up to execute the method according to one of the preceding claims and to connect the inverter to a connected grid only if a fault state is not identified.