The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Feb. 26, 2020
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Mitsuhito Kanatake, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H10F 39/804 (2025.01); H01L 21/56 (2013.01); H01L 24/48 (2013.01); H10F 39/811 (2025.01); H01L 2224/48228 (2013.01); H01L 2224/48453 (2013.01); H01L 2224/48463 (2013.01); H01L 2924/182 (2013.01); H01L 2924/18301 (2013.01); H01L 2924/186 (2013.01); H10F 39/809 (2025.01);
Abstract

To arrange a protective material horizontally with respect to a substrate plane without the protective material coming into contact with wires in a wire-bonded semiconductor package. The semiconductor package includes a protective material, a substrate, bumps, and a semiconductor chip. The bumps are provided on a chip plane of the semiconductor chip and are connected to the substrate via wires. The semiconductor chip is laminated on the substrate. A support is provided on the chip plane to support the protective material at a position where the height from the chip plane of the semiconductor chip is higher than the bumps.


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