The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

May. 17, 2024
Applicant:

Nanya Technology Corporation, New Taipei, TW;

Inventor:

Jhen-Yu Tsai, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/17 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10B 12/33 (2023.02); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 21/764 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 30/031 (2025.01); H10D 30/6728 (2025.01); H10D 30/6735 (2025.01); H10D 30/6755 (2025.01); H10D 62/292 (2025.01); H10D 99/00 (2025.01);
Abstract

A semiconductor device includes a first vertical transistor and a second vertical transistor adjacent to the first vertical transistor. The first vertical transistor includes a first channel region, a first word line wrapping the first channel region, and a first word line dielectric layer between the first channel region and the first word line. The second vertical transistor includes a second channel region, a second word line wrapping the second channel region, and a second word line dielectric layer between the second channel region and the second word line. The semiconductor device further includes a dielectric layer wrapping upper portions of the first word line and the second word line, and an air gap inserted between lower portions of the first vertical transistor and the second vertical transistor.


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