The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jul. 18, 2023
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Chien-Wei Chen, Hsinchu, TW;

Kairen Fong, Hsinchu, TW;

Chao-Ching Hung, Hsinchu, TW;

Yu-Li Hsueh, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); G04F 10/00 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 5/01 (2013.01); G04F 10/005 (2013.01); H03K 3/037 (2013.01);
Abstract

A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.


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