The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Aug. 23, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyung Min Ko, Seoul, KR;

Myung Hun Lee, Seongnam-si, KR;

Pan Suk Kwak, Goyang-si, KR;

Dae Seok Byeon, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H01L 29/42324 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.


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