The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Dec. 07, 2023
Applicant:

Fabric8labs, Inc., San Diego, CA (US);

Inventors:

David Pain, Carlsbad, CA (US);

Andrew Edmonds, Oceanside, CA (US);

Jeffrey Herman, Solana Beach, CA (US);

Charles Pateros, Carlsbad, CA (US);

Kareemullah Shaik, San Diego, CA (US);

Assignee:

FABRIC8LABS, INC., San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); B33Y 10/00 (2015.01); B33Y 30/00 (2015.01); B33Y 50/02 (2015.01); B33Y 80/00 (2015.01); C25D 1/00 (2006.01); C25D 5/10 (2006.01); C25D 5/22 (2006.01);
U.S. Cl.
CPC ...
H01L 21/485 (2013.01); C25D 1/003 (2013.01); C25D 5/10 (2013.01); C25D 5/22 (2013.01); H01L 21/4825 (2013.01); H01L 21/4882 (2013.01); B33Y 10/00 (2014.12); B33Y 30/00 (2014.12); B33Y 50/02 (2014.12); B33Y 80/00 (2014.12);
Abstract

A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 μm or more, diameters of 10 μm or below, and inter-pillar spacing below 20 μm. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.


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