The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Feb. 14, 2024
Applicant:

Rebellions Inc., Seongnam-si, KR;

Inventor:

Jinwook Oh, Seongnam-si, KR;

Assignee:

Rebellions Inc., Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/06 (2006.01); G06F 9/50 (2006.01); G06F 13/14 (2006.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/5011 (2013.01); G06F 13/14 (2013.01); G06F 2209/501 (2013.01); G06F 2209/508 (2013.01);
Abstract

A neural processing device is provided. The neural processing device includes a plurality of processing engine groups, a first memory shared by the plurality of engine groups, a first interconnection configured to transmit data between the first memory and the plurality of processing engine groups. The neural processing device is configured to provide hardware resource to the plurality of processing engine groups. At least one of the plurality of processing engine groups includes a plurality of processing engines, each of the plurality of processing engines includes an array of a plurality of processing elements interconnected by a mesh style network, the processing elements being reconfigurable. The neural processing device includes a second memory shared by the plurality of processing engines, and a second interconnection configured to transmit data between the second memory and the plurality of processing engines.


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