The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Feb. 28, 2023
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Raphaël Millet, Gif-sur-Yvette, FR;

Benoit Tain, Gif-sur-Yvette, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/345 (2018.01); G06F 9/355 (2018.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 17/15 (2006.01); G06N 3/0464 (2023.01); G06N 3/063 (2023.01);
U.S. Cl.
CPC ...
G06F 9/345 (2013.01); G06F 12/02 (2013.01); G06F 12/0207 (2013.01); G06F 17/153 (2013.01); G06F 9/355 (2013.01); G06F 12/0607 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/454 (2013.01); G06N 3/0464 (2023.01); G06N 3/063 (2013.01);
Abstract

An address generator for a computer with a single instruction multiple data architecture includes a plurality of elementary processors each associated with a local memory, each elementary processor having access to its local memory and at least one access to a neighbouring local memory of another elementary processor, the address generator configured, in response to a computing instruction, to determine an identical memory access address for all the elementary processors, the address generator including: a first computing unit for computing a first access offset value in a first addressing dimension, and an adder for computing the memory access address as the sum of the first access offset value and of a predetermined initial offset value dependent on a memory access operation type indicated by the computing instruction from among a memory access operation to the local memory or a memory access operation to any of the neighbouring local memories.


Find Patent Forward Citations

Millet, Raphaël. (2025). Address generator using memory access operation type for a computer with a single instruction multiple data architecture (U.S. Patent No. 12307255). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12307255

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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