The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

May. 06, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Eric F. Dellinger, Longmont, CO (US);

Philip B. James-Roxby, Longmont, CO (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01); G06F 7/499 (2006.01); H03M 7/24 (2006.01); H03M 7/30 (2006.01);
U.S. Cl.
CPC ...
G06F 7/483 (2013.01); G06F 7/49942 (2013.01); H03M 7/24 (2013.01); H03M 7/30 (2013.01);
Abstract

Approaches for compressing exponents of floating point values include accumulating a distribution of values of exponents of the first set of floating point values, and compressing the exponents of the first set of floating point values into a compressed exponent bit-width as a function of a compressed exponent bias. The compressed exponent bit-width and the compressed exponent bias are adjusted based on the distribution of values of exponents of the first set of floating point values. The distribution of values of exponents of the first set of floating point values is accumulated with values of exponents of a second set of floating point values that is input in subsequent time period. The exponents of second set of floating point values are compressed into the compressed exponent bit-width as a function of the compressed exponent bias after the adjusting of the compressed exponent bit-width and the compressed exponent bias.


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