The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Nov. 22, 2021
Michele Mosca, Waterloo, CA;
softwareQ Inc., Waterloo, CA;
Abstract
The present application recognizes the problem of reducing the CNOT-count in Clifford+T circuits on connectivity constrained architectures. Here, one can 'slice' the circuit at the position of Hadamard (H) gates and “build” the intermediate portions. Two kinds of partitioning are evaluated, namely: (i) a simple method of partitioning the gates of the input circuit based on the locality of H gates, and (ii) a second method of partitioning the phase polynomial of the input circuit. The intermediate {CNOT, T} sub-circuits can be synthesized using Steiner trees, similar to the work of Nash, Gheorghiu, Mosca [NGM20] and Kissinger, de Griend [KdG19]. The following algorithms have certain procedural differences that also help to further reduce the CNOT-count. The performances of the algorithms are compared while mapping different benchmark circuits as well as random circuits to some popular architectures like 9-qubit square grid, 16-qubit square grid, Rigetti 16qubit Aspen, 16-qubit IBM QX5, 20-qubit IBM Tokyo.