The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Sep. 08, 2023
Applicant:

Coherent Logix, Incorporated, Austin, TX (US);

Inventors:

Carl S. Dobbs, Austin, TX (US);

Michael R. Trocino, Austin, TX (US);

Assignee:

HyperX Logic, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 9/4401 (2018.01); G06F 13/16 (2006.01); G06F 13/362 (2006.01); G06F 13/42 (2006.01); G06F 15/173 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1652 (2013.01); G06F 9/4401 (2013.01); G06F 13/362 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 15/17381 (2013.01); G06F 15/7817 (2013.01); G06F 15/7882 (2013.01); Y02D 10/00 (2018.01);
Abstract

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.


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