The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Dec. 20, 2022
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Jagadish B. Kotra, Austin, TX (US);
John Kalamatianos, Arlington, MA (US);
Paul James Moyer, Fort Collins, CO (US);
Nicholas Dean Lance, Windsor, CO (US);
Sriram Srinivasan, Cedar Park, TX (US);
Patrick James Shyvers, Fort Collins, CO (US);
William Louie Walker, Fort Collins, CO (US);
Advanced Micro Devices, Inc, Santa Clara, CA (US);
Abstract
An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.