Min-sum decoding for irregular low-density parity check codes in memory devices

Abstract

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular low-density parity-check (LDPC) code, performing, in a first mode of the iterative decoder and on the noisy codeword for a number of iterations, a message passing algorithm between multiple variable nodes and multiple check nodes that represent a parity matrix of the irregular LDPC code, and determining, subsequent to performing the number of iterations, a candidate version of the transmitted codeword. In this first mode, and as part of performing the message passing algorithm, at least one check node of the multiple check nodes is configured to store a portion of multiple check node parameters instead of all of the multiple check node parameters.