The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Dec. 12, 2024
Xi'an Xd Power Systems Co., Ltd., Xi'an, CN;
China Xd Electric Co., Ltd., Xi'an, CN;
Liguo Chang, Xi'an, CN;
Yantao Lou, Xi'an, CN;
Xiaogang Tu, Xi'an, CN;
Hengyu Zhang, Xi'an, CN;
Xiaoting Ma, Xi'an, CN;
Hongchang Tian, Xi'an, CN;
Jun Hong, Xi'an, CN;
Yu Wang, Xi'an, CN;
XI'AN XD POWER SYSTEMS CO., LTD., Xi'an, CN;
CHINA XD ELECTRIC CO., LTD., Xi'an, CN;
Abstract
The present disclosure discloses a method and apparatus for controlling redundancy of a valve control system of a converter valve. The method includes: for each FPGA: in a case that the FPGA receives the on-duty state representing the active state: outputting a high-level control signal to a data selector through the FPGA; in a case that the FPGA receives the on-duty state representing the standby state: outputting a low-level control signal to the data selector through the FPGA, and maintaining a control signal output state of the FPGA and the other FPGA; and in a case that running state information of the other FPGA received by the FPGA through a monitoring output channel is a crash state: outputting a low-level signal to a control port of the other FPGA through the monitoring output channel by the FPGA.