The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Jun. 20, 2023
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Moonho Park, Gyeonggi-do, KR;

Sangsoon Noh, Gyeonggi-do, KR;

Dongchae Shin, Gyeonggi-do, KR;

Sunyoung Choi, Gyeonggi-do, KR;

Mijin Jeong, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/121 (2023.01); G06F 3/041 (2006.01); G06F 3/044 (2006.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H10K 59/40 (2023.01); H10K 59/80 (2023.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); G06F 3/0412 (2013.01); G06F 3/0446 (2019.05); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 59/40 (2023.02); H10K 59/873 (2023.02); G09G 3/3233 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01);
Abstract

A thin film transistor, in one or more examples, includes a semiconductor layer, an upper gate electrode overlapped with the semiconductor layer, an upper insulating layer disposed between the semiconductor layer and the upper gate electrode, a first lower gate electrode overlapped with the semiconductor layer, a second lower gate electrode disposed between the semiconductor layer and the first lower gate electrode, overlapped with the semiconductor layer, and configured to have a width smaller than that of the upper gate electrode, a first lower insulating layer disposed between the first lower gate electrode and the second lower gate electrode, and a second lower insulating layer disposed between the second lower gate electrode and the semiconductor layer. A display apparatus including a thin film transistor is also disclosed.


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