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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12302580 B1

PDFFull Text
Date of Patent:
May. 13, 2025

Filed:

Apr. 15, 2021

Semiconductor devices and data storage systems including the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sanghun Chun, Suwon-si, KR;

Jihwan Kim, Suwon-si, KR;

Shinhwan Kang, Suwon-si, KR;

Jeehoon Han, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Shaun M Campbell

Assistant Examiner:

Carnell Hunter, Iii

Int. Cl.
CPC ...
H10B 43/50 (2023.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/50 (2023.02); H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor memory device includes a first substrate; active or passive circuits on the first substrate; a second substrate above the active or passive circuits; gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction; channel structures penetrating through the gate electrodes and extending in the first direction, and each including a channel layer; separation regions penetrating through the gate electrodes and extending in a second direction; a through-contact plug extending through the second substrate in the first direction and electrically connecting the gate electrodes and the active or passive circuits to each other; and a barrier structure spaced apart from the through-contact plug and surrounding the through-contact plug and having first regions each having a first width, and second regions each having a second width greater than the first width.

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