The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Dec. 10, 2021
Applicants:

Posi Energy-silicon Power, Llc, Pleasantville, NY (US);

Devendra K. Sadana, Pleasantville, NY (US);

Inventor:

Devendra K. Sadana, Pleasantville, NY (US);

Assignee:

POSI ENERGY—SILICON POWER, LLC, Pleasantville, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01M 4/38 (2006.01); H01M 4/02 (2006.01); H01M 4/04 (2006.01); H01M 4/134 (2010.01); H01M 4/36 (2006.01); H01M 4/66 (2006.01); H01M 10/0525 (2010.01);
U.S. Cl.
CPC ...
H01M 4/386 (2013.01); H01M 4/0426 (2013.01); H01M 4/134 (2013.01); H01M 4/366 (2013.01); H01M 4/382 (2013.01); H01M 4/661 (2013.01); H01M 10/0525 (2013.01); H01M 2004/021 (2013.01); H01M 2300/0091 (2013.01);
Abstract

Methods for minimizing or eliminating cracks in the crystalline porous-Si structure that can occur during the layer release process and/or during subsequent processing in a lithium-ion battery during charge and discharge cycles. The methods include: modifying the anodic etching process so that a freestanding film of Si with the anode structure is detached from a p-doped substrate; depositing a conductive layer on the back surface of the released porous-Si structure with or without a metallic seed layer; mechanically or chemically thinning the back surface of the Si substrate after forming the porous-Si at the front surface of a thick Si substrate; forming a thin crystalline porous-Si anode structure on a p-doped silicon epitaxy grown on porous-Si with a porous-Si release layer.


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