The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Jan. 25, 2022
Applicant:

Infinera Corp., Sunnyvale, CA (US);

Inventors:

John W. Osenbach, Kutztown, PA (US);

Jiaming Zhang, Macungie, PA (US);

Assignee:

Infinera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/64 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 23/642 (2013.01); H01L 28/40 (2013.01);
Abstract

Disclosed herein are multi-layer substrates for integrated circuit packages and methods of making the same. The multi-layer substrate may comprise a plurality of lower layers, at least one core layer, a plurality of upper layers, and a side surface. A first connection and a second connection may extend through or on an uppermost layer of the plurality of upper layers. A trace may be embedded in or on one of the plurality of upper layers, the trace electrically connected to the first connection and the second connection. A first mounting pad and a second mounting pad may be positioned on the side surface and/or the uppermost layer of the plurality of upper layers and a blocking capacitor may be electrically connected to the first mounting pad and the second mounting pad with the second mounting pad electrically connected to the second connection.


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