The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Mar. 03, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Masahiro Saito, Tokyo, JP;

Kiwamu Watanabe, Kawasaki Kanagawa, JP;

Yuko Noda, Kawasaki Kanagawa, JP;

Tsukasa Tokutomi, Kamakura Kanagawa, JP;

Yoshiki Takai, Fujisawa Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01);
Abstract

A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.


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