The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Oct. 21, 2022
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Vianney Antoine Choserot, Antibes, FR;

Andy Wangkun Chen, Austin, TX (US);

Yew Keong Chong, Austin, TX (US);

Sriram Thyagarajan, Austin, TX (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.


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