The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Oct. 26, 2023
Applicant:

Weka.io Ltd, Tel Aviv, IL;

Inventors:

Maor Ben Dayan, Tel Aviv, IL;

Omri Palmon, Tel Aviv, IL;

Liran Zvibel, Tel Aviv, IL;

Kanael Arditti, Tel Aviv, IL;

Assignee:

Weka.IO Ltd., , IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 16/182 (2019.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0643 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 16/182 (2019.01);
Abstract

A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. The plurality of computing devices maintains metadata that maps each failure resilient address space to one of the plurality of computing devices. Each of the plurality of computing devices is operable to read from and write to a plurality of memory blocks, while maintaining an extent in metadata that maps the plurality of memory blocks to the failure resilient address space.


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