The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Apr. 21, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Paul Robert Schumacher, Berthoud, CO (US);

Anurag Dubey, Boulder, CO (US);

Roger Ng, Campbell, CA (US);

Ishita Ghosh, San Jose, CA (US);

Scott H. Jonas, Niwot, CO (US);

Krishnan Subramanian, San Jose, CA (US);

Jason Richard Villarreal, Los Gatos, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/36 (2006.01); G06F 11/34 (2006.01); G06F 11/362 (2025.01);
U.S. Cl.
CPC ...
G06F 11/3636 (2013.01); G06F 11/348 (2013.01);
Abstract

Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.


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