The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Apr. 18, 2024
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Guangcai Yuan, Beijing, CN;

Hehe Hu, Beijing, CN;

Ce Ning, Beijing, CN;

Hui Guo, Beijing, CN;

Fengjuan Liu, Beijing, CN;

Dongfang Wang, Beijing, CN;

Zhengliang Li, Beijing, CN;

Jiayu He, Beijing, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/136209 (2013.01); G02F 1/136213 (2013.01); G02F 1/136227 (2013.01); G02F 1/136295 (2021.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01);
Abstract

An array substrate and a manufacturing method therefor, and a display apparatus are provided. The array substrate includes an underlay substrate, and at least one first transistor, at least one data line and at least one pixel electrode disposed on the underlay substrate. The at least one first transistor includes a first active layer and a first gate; the first gate is located on a side of the first active layer away from the underlay substrate, and orthographic projections of the first gate and the first active layer on the underlay substrate are at least partially overlapped. The first active layer is electrically connected to the data line and the pixel electrode, respectively. The data line is located on a side of the first active layer close to the underlay substrate, and the pixel electrode is located on a side of the first gate away from the underlay substrate.


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