The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Dec. 10, 2021
Applicant:

Quantum-si Incorporated, Guilford, CT (US);

Inventor:

Eric A. G. Webster, Santa Clara, CA (US);

Assignee:

Quantum-Si Incorporated, Branford, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
C12Q 1/6869 (2018.01); G01N 21/64 (2006.01); H01L 27/146 (2006.01); H01L 27/148 (2006.01); H01S 3/1112 (2023.01);
U.S. Cl.
CPC ...
C12Q 1/6869 (2013.01); G01N 21/6408 (2013.01); G01N 21/6428 (2013.01); G01N 21/6458 (2013.01); H01L 27/14609 (2013.01); H01L 27/14806 (2013.01); H01L 27/14818 (2013.01); H01S 3/1112 (2013.01); G01N 2201/06113 (2013.01); G01N 2201/0697 (2013.01);
Abstract

The present disclosure provides techniques for improving the rate and efficiency of charge transfer within an integrated circuit configured to receive incident photons. Some aspects of the present disclosure relate to integrated circuits that are configured to induce one or more intrinsic electric fields that increase the rate and efficiency of charge transfer within the integrated circuits. Some aspects of the present disclosure relate to integrated circuits configured to induce a charge carrier depletion in the photodetection region(s) of the integrated circuits. In some embodiments, the charge carrier depletion in the photodetection region(s) may be intrinsic, in that the depletion is induced even in the absence of external electric fields applied to the integrated circuit. Some aspects of the present disclosure relate to processes for operating and/or manufacturing integrated devices as described herein.


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