The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Apr. 08, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Yoonsun Choi, Hwaseong-si, KR;

Seong Ryong Lee, Hwaseong-si, KR;

Hyun Chul Kim, Hwaseong-si, KR;

Seongjun Lee, Seoul, KR;

Eunae Jung, Hwaseong-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2022.12); G09G 3/20 (2005.12); G09G 3/3233 (2015.12); G09G 3/3291 (2015.12); G09G 3/36 (2005.12); H10K 50/844 (2022.12); H10K 59/122 (2022.12); H10K 59/40 (2022.12); H10K 71/00 (2022.12);
U.S. Cl.
CPC ...
H10K 59/131 (2023.01); G09G 3/3291 (2012.12); H10K 50/8445 (2023.01); H10K 59/122 (2023.01); H10K 59/40 (2023.01); G09G 2300/0426 (2012.12); G09G 2300/0439 (2012.12);
Abstract

An organic light-emitting display device includes a base substrate, a pixel array, a first power voltage wiring and a second power voltage wiring. The base substrate includes a pixel area and a peripheral area. The pixel array is disposed in the pixel area. The first power voltage wiring is disposed in the peripheral area and includes a first lower power voltage line and a first upper power voltage line. The first upper power voltage line is disposed on and contacts the first lower power voltage line. The second power voltage wiring is disposed in the peripheral area and includes a second lower power voltage line and a second upper power voltage line. The second upper power voltage line is disposed on and contacts the second lower power voltage line. The first upper power voltage line overlaps the second lower power voltage line in a plan view.


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