The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Nov. 20, 2020
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventors:

Yu Saitoh, Osaka, JP;

Takeyoshi Masuda, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2024.12); H01L 21/04 (2005.12); H10D 12/01 (2024.12); H10D 30/66 (2024.12); H10D 62/17 (2024.12); H10D 62/832 (2024.12);
U.S. Cl.
CPC ...
H10D 62/109 (2024.12); H01L 21/046 (2012.12); H10D 12/031 (2024.12); H10D 30/668 (2024.12); H10D 62/393 (2024.12); H10D 62/8325 (2024.12);
Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. A gate trench is provided in the first main surface. The gate trench is defined by side surfaces and a bottom surface. The side surfaces penetrate the source region and the body region to reach the drift region. The bottom surface connects to the side surfaces. The gate trench extends in a first direction parallel to the first main surface. The silicon carbide substrate further includes an electric field relaxation region that is the second conductive type, the electric field relaxation region being provided between the bottom surface and the second main surface and extending in the first direction, and a connection region that is the second conductive type, the connection region electrically connecting a contact region to the electric field relaxation region. In a plan view in a direction normal to the first main surface, the gate trench and the electric field relaxation region are disposed on a virtual line that extends in the first direction, and the connection region is in contact with the electric field relaxation region on the virtual line.


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