The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2025
Filed:
Oct. 04, 2021
Applicant:
Sony Corporation, Tokyo, JP;
Inventor:
Takuji Matsumoto, Kanagawa, JP;
Assignee:
SONY CORPORATION, Tokyo, JP;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2005.12); H01L 29/08 (2005.12); H01L 29/165 (2005.12); H01L 29/417 (2005.12); H01L 29/45 (2005.12); H01L 29/66 (2005.12); H10D 30/01 (2024.12); H10D 30/60 (2024.12); H10D 30/69 (2024.12); H10D 62/00 (2024.12); H10D 62/13 (2024.12); H10D 62/822 (2024.12); H10D 64/01 (2024.12); H10D 64/23 (2024.12); H10D 64/62 (2024.12); H10D 84/01 (2024.12); H10D 84/03 (2024.12); H10D 84/83 (2024.12); H01L 21/8238 (2005.12); H01L 27/088 (2005.12);
U.S. Cl.
CPC ...
H10D 30/797 (2024.12); H10D 30/015 (2024.12); H10D 30/603 (2024.12); H10D 30/608 (2024.12); H10D 30/792 (2024.12); H10D 62/021 (2024.12); H10D 62/151 (2024.12); H10D 62/822 (2024.12); H10D 64/021 (2024.12); H10D 64/259 (2024.12); H10D 64/62 (2024.12); H10D 84/0167 (2024.12); H10D 84/017 (2024.12); H10D 84/038 (2024.12); H10D 84/83 (2024.12); H10D 30/0212 (2024.12);
Abstract
A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.