The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Sep. 01, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Katsuyoshi Komatsu, Yokkaichi Mie, JP;

Hiroki Tokuhira, Kawasaki Kanagawa, JP;

Hiroshi Takehira, Yokkaichi Mie, JP;

Hiroyuki Ode, Yokkaichi Mie, JP;

Jieqiong Zhang, Yokkaichi Mie, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2022.12); G11C 13/00 (2005.12); H10N 70/00 (2022.12); H10N 70/20 (2022.12);
U.S. Cl.
CPC ...
H10B 63/845 (2023.01); G11C 13/0004 (2012.12); G11C 13/004 (2012.12); G11C 13/0069 (2012.12); H10B 63/20 (2023.01); H10N 70/066 (2023.01); H10N 70/231 (2023.01); G11C 2213/71 (2012.12); G11C 2213/72 (2012.12);
Abstract

A semiconductor memory device includes a first wiring extending in a first direction; a second wiring extending in a second direction and spaced from the first wiring in a third direction; a stacked body disposed between the first and second wirings and including conductive layers and insulating layers alternately stacked on top of one another in the third direction; a columnar body extending through the stacked body and including: (a) an electrode disposed between the first wiring and the second wiring, (b) a memory layer disposed between the electrode and the conductive layers, and (c) a selection layer disposed between the electrode and the first wiring; and a diode disposed between the electrode and the second wiring.


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