The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Apr. 26, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Takeo Yasuda, Nara, JP;

Robert K. Montoye, Yorktown Heights, NY (US);

Gerald W. Gibson, Danbury, CT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/195 (2005.12); G06F 1/06 (2005.12); H03K 5/00 (2005.12); H03K 5/01 (2005.12);
U.S. Cl.
CPC ...
H03K 19/195 (2012.12); G06F 1/06 (2012.12); H03K 5/01 (2012.12); H03K 2005/00078 (2012.12);
Abstract

Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.


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