The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 06, 2025

Filed:

Oct. 07, 2020
Applicant:

Zero-error Systems Pte. Ltd, Singapore, SG;

Inventors:

Joseph Sylvester Chang, Singapore, SG;

Wei Shu, Singapore, SG;

Yong Qu, Singapore, SG;

Kwen Siong Chong, Singapore, SG;

Arunjai Mittal, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2005.12); H03K 3/037 (2005.12); H03K 17/687 (2005.12); H03K 19/003 (2005.12);
U.S. Cl.
CPC ...
H03K 19/00338 (2012.12); G11C 7/1069 (2012.12); G11C 7/1096 (2012.12); H03K 3/0375 (2012.12); H03K 17/6872 (2012.12);
Abstract

A circuit for mitigating single-effect-transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to generate a first output and a first n-type transistor arrangement configured to generate a second output; and a second sub-circuit comprising a connecting p-type transistor arrangement and a connecting n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other through the second sub-circuit.


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